Candidate Subcircuits for Functional Module Identification in Logic Circuits

Authors

Jennifer L. White
Anthony S. Wojcik
Moon-Jung Chung
Travis E. Doom, Wright State University - Main CampusFollow

Document Type

Conference Proceeding

Publication Date

3-2000

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Abstract

Recovering functional information from existing hardware is a difficult problem in design automation. However, it is an important focus for designers attempting to redesign for expanded functionality or superior performance. Often, the only reliable information available about a piece of digital hardware is the hardware itself. Documentation, even if it is available, may be outdated or incorrect. Existing procedures are able to recover the transistor-level netlist, or a gate-level netlist from an existing implementation. The next step in this process is the gate-level to module-level transformation, the focus of this paper. We have designed a technique to enumerate all of the potential modules within a gate-level netlist so that their functional equivalence to known modules may be evaluated.

Comments

Presented at the 10th Great Lakes Symposium on VLSI, Evanston, IL, March 2-4, 2000.

Repository Citation

White, J. L., Wojcik, A. S., Chung, M., & Doom, T. E. (2000). Candidate Subcircuits for Functional Module Identification in Logic Circuits. Proceedings of the 10th Great Lakes Symposium on VLSI, 34-38.
https://corescholar.libraries.wright.edu/cse/286

DOI

10.1145/330855.332575