Publication Date
2014
Document Type
Thesis
Committee Members
J.M. Emmert (Advisor), Saiyu Ren (Committee Member), Raymond Siferd (Committee Member)
Degree Name
Master of Science in Engineering (MSEgr)
Abstract
As fabrication technologies improve logic densities increase. It becomes harder to mitigate clock skew and jitter. Higher clock rates combined with increased numbers of sinks increase mixed-system substrate noise. An increasingly popular approach to address these problems is clockless logic. One technique is Null Convention Logic (NCL). However, traditional NCL feedback loops have large area overhead and require many gate delays. This makes NCL impractical in many applications. In this paper we propose to replace the feedback logic with a two-stage voltage divider. Using our technique we show up to 50% area reduction and require only one unit gate delay.
Page Count
60
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2014
Copyright
Copyright 2014, all rights reserved. This open access ETD is published by Wright State University and OhioLINK.
