Publication Date
2014
Document Type
Thesis
Committee Members
Chien-in Chen (Advisor), Marian Kazimierczuk (Committee Member), Yan Zhuang (Committee Member)
Degree Name
Master of Science in Engineering (MSEgr)
Abstract
A System-on-a-Chip (SoC) has millions of transistors connected by wires or so called Interconnects. As CMOS technologies scale down, SoC becomes more complex and denser. The delays of basic cells decrease, hereby improving logic gate and logic block delay. However, long wires connecting logic blocks still contribute significant delays, which limit SoC's speed performance.
In this thesis, we take a practical approach towards reducing propagation delay in long wire (Interconnect). A dynamic repeater with Booster enhancement circuit is presented and analyzed in this regard. Both switching speed and Interconnect propagation delay are significantly improved upon locally enabling the Booster to operate as a pull-up and pull-down circuit for every repeater stage. Using the repeater and Booster enhancement circuit on a 5 mm long wire in 180 nanometer CMOS technology, the average switching speed is improved by 27% and the propagation delay is improved by about 46%.
Page Count
72
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2014
Copyright
Copyright 2014, all rights reserved. This open access ETD is published by Wright State University and OhioLINK.
