Soon Chung (Committee Member), Jack Jean (Committee Member), Meilin Liu (Advisor)
Master of Science in Computer Engineering (MSCE)
As the power consumption (power wall) is limiting the clock frequency increase, multi-core and many-core processors become the major-trend of the new generation of processors. One of the biggest challenges to achieve high performance in multi-core systems is the growing disparity between processor and memory speeds. The "memory wall"' problem, i.e., the growing disparity of speed between the processor and the memory, becomes even more serious in the multi-core systems. Caches have been highly successful in bridging the processor-memory performance gap by providing fast access to frequently used data. Caches also save power by limiting expensive off-chip memory accesses. In this thesis, we propose an Adaptive Bloom Filter Cache Partitioning Scheme to improve both temporal locality and spatial locality and to take advantage of the memory hierarchy in the multi-core systems. We use multi2Sim, a multi-core simulator, to collect the memory traces for the test benchmarks. The collected memory traces were used as the test inputs for the proposed dynamic cache partitioning scheme. The simulation results showed that the cache misses were reduced significantly by the proposed dynamic Cache Partitioning scheme.
Department or Program
Department of Computer Science and Engineering
Year Degree Awarded
Copyright 2014, some rights reserved. My ETD may be copied and distributed only for non-commercial purposes and may not be modified. All use must give me credit as the original author.
Creative Commons License
This work is licensed under a Creative Commons Attribution-Noncommercial-No Derivative Works 3.0 License.