Publication Date
2016
Document Type
Thesis
Committee Members
John Marty Emmert (Advisor), Saiyu Ren (Committee Member), Raymond Siferd (Committee Member)
Degree Name
Master of Science in Electrical Engineering (MSEE)
Abstract
Semiconductor integrated circuits (ICs) have become key components in almost every aspect of our daily lives. From simple home appliances to extremely sophisticated aerospace systems, we have become increasingly dependent on ICs. System-on-chip (SoC) is an IC methodology that includes multiple design technologies on a single IC chip. SoC was developed to further integrate and manage system complexity. Due to SoC and increasingly dense IC fabrication technologies, design time and thereby system time-to-market are becoming more critical drivers of the IC design cycle. In order to address issues related to design time and time-to-market, highly optimized semiconductor intellectual property (IP) is often leveraged. These IP blocks are predesigned, highly optimized sub-system components. To take full advantage of these and other sub-components, we have developed a Genetic Algorithm (Simulated Evolution) based floorplanning tool to quickly and efficiently solve the SoC and application specific integrated circuit (ASIC) floorplanning problem. Our tool takes advantage of both hard and soft macros to optimize IC area usage.
Page Count
50
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2016
Copyright
Copyright 2016, some rights reserved. My ETD may be copied and distributed only for non-commercial purposes and may be modified only if the modified version is distributed with these same permissions. All use must give me credit as the original author.
Creative Commons License
This work is licensed under a Creative Commons Attribution-Noncommercial-Share Alike 3.0 License.
