Publication Date


Document Type


Committee Members

Saiyu Ren (Advisor), Ray Siferd (Committee Member), Marian K. Kazimierczuk (Committee Member)

Degree Name

Master of Science in Electrical Engineering (MSEE)


Many wired and wireless communication systems require high-speed and high-performance data converters. These data converters act as bridge between digital signal processing blocks and power amplifiers. However, these data converters have been the bottleneck in the communication systems. This thesis presents the design of a 10-bit C2C digital to analog converter (DAC) for high resolution, wide bandwidth and low power consumption applications. The DAC is implemented in CMOS 65nm technology. The SFDR of this C2C DAC is 71.95dB at 500MHz input frequency and consumes 88.14µW of power with ENOB as 11.65 with 1.0GHz sample frequency with 0.31LSB of INL and 0.5LSB of DNL. A 10-bit SAR ADC is designed using this proposed C2C DAC with 427.4µW of power consumption at 1.0V voltage supply.

Page Count


Department or Program

Department of Electrical Engineering

Year Degree Awarded