Henry Chen (Advisor), Marian Kazimierczuk (Committee Member), Yan Zhuang (Committee Member)
Master of Science in Engineering (MSEgr)
Dynamic CMOS are widely employed in high-performance CMOS chips due to high speed and less area in comparison with Static CMOS. However, Dynamic CMOS circuits are inherently less noise tolerant than Static CMOS circuits. This problem becomes more severe with aggressive technology scaling into nanometer process, particularly caused by the charge sharing, the sub-threshold leakage current, the power rail noise and the crosstalk noise. In this thesis, circuit techniques on improving both timing and noise of Dynamic CMOS are presented. A comparison with previous reported work is also presented. Simulations proved that the proposed circuit techniques can achieve a high level of timing optimization and noise tolerance. Finally, the effect of manufacturing process variations is taken into simulation to verify overall performance variation in delay uncertainty
Department or Program
Department of Electrical Engineering
Year Degree Awarded
Copyright 2011, all rights reserved. This open access ETD is published by Wright State University and OhioLINK.