The dawn of tunnel diodes, commonly attributed to Leo Esaki in the late 1950’s, predates much of the innovation and infrastructure investment into CMOS technology. But, the lack of a mass production process and inability to monolithically integrate these devices into complex circuits paved the way for the CMOS juggernaut seen today.
However, the unique negative differential resistance (NDR) systemic to all tunnel diodes provides a pathway to exploit new hybrid-CMOS circuit topologies with compact latches and reduced power consumption that could mitigate some of the bottlenecks perceived for scaled CMOS. A new paradigm of computing is possible, capitalizing upon transistor/tunnel diode integration if a viable Si-based tunnel diode could be developed. This talk will explore these opportunities.
This talk will provide a background on Si-based tunnel diode devices and circuits and summarize the results of Si-based RITD device optimization, their monolithic integration with Si-based transistors and present a range of circuit prototyping. The extension of NDR to ultra-low voltage memory will also be discussed.
Quantum functional circuitry exploiting negative differential resistance (NDR) devices offers a paradigm shift in computational architectures for a multitude of circuitries (low-power embedded memory, mixed-signal and logic), that enables continued Si/SiGe scaling according to Moore’s Law. The advantage of quantum functional circuits is illustrated by the N-shaped electrical characteristics of two serially connected NDR devices which can be exploited to easily fashion two stable latching points. NDR-based circuitry facilitates simple circuit topologies to fashion latches etc., permitting tunnel diode/transistor circuits that require fewer devices, less chip area and reduced power consumption
We will present results on room temperature NDR devices and circuits using a Si-based resonant interband tunnel diode (RITD) developed by this team that is a hybrid NDR device that uses quantum wells formed by delta-doping and appropriate band offsets to facilitate robust tunneling across a p-n junction. This talk will illustrate this pathway for silicon, and then this will be extended to conjugated polymer based devices that are in their initial investigations.
The polymer device to be presented leverages the unique flexible and solution-processable properties of conjugated polymer semiconductors. We will demonstrate robust room temperature negative differential resistance and logic circuit operations using polymer tunnel diodes (ITO/TiO2/MEH-PPV/Al), suitable for SmartCard topologies.
Berger , P. R. (2013). Plastic Low-Cost Circuits Enabled Through Nanotechnology. .