Publication Date
2015
Document Type
Thesis
Committee Members
John Emmert (Committee Member), Saiyu Ren (Advisor), Raymond Siferd (Committee Member)
Degree Name
Master of Science in Engineering (MSEgr)
Abstract
Digital analog converters bridge the gap between digital signal processing chips, and power amplifiers that transmit analog signals. Communications systems require ever increasing bandwidth, however data converters are typically the bottleneck in these systems. This thesis presents the design of a high speed current steering DAC using CMOS 90 nm technology. The resolution of the converter is 10 bits, segmented into 6 thermometer encoded MSB current cells, and 4 binary weighted LSB current cells. Each of the sub-components, such as the binary-thermometer encoder, digital latch, current cell, reconstruction filter, are discussed in detail. The current cells were designed with transistor matching, and output impedance effects in mind to achieve high performance. The DNL of the converter was measured to be 0.02 LSB, while the INL is 0.29 LSB. With a clock frequency of 1.2 GHz, the SFDR was measured to be 72.07 dB with an input of 596.48 MHz.
Page Count
82
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2015
Copyright
Copyright 2015, some rights reserved. My ETD may be copied and distributed only for non-commercial purposes and may not be modified. All use must give me credit as the original author.
Creative Commons License
This work is licensed under a Creative Commons Attribution-Noncommercial-No Derivative Works 3.0 License.
