Candidate Subcircuit Generation to Facilitate Identification of High-Level Components in Logic Circuits

Authors

Jennifer L. White
Travis E. Doom, Wright State University - Main CampusFollow
Anthony S. Wojcik
Moon-Jung Chung
Greg Chisholm

Document Type

Report

Publication Date

12-1997

Abstract

Recovering the design of a circuit involves raising the level of abstraction from a flat netlist to a more easily understood modular level. Efficient algorithms exist to locate gate clusters (subcircuits) that are syntactically equivalent to known modules, but such technology will fail to match semantically equivalent subcircuits that differ in implementation. This paper discusses the problem of generating the candidate subcircuits so that their equivalence to a known high level module can be examined.

Comments

Technical Report MSU-CPS-97-48

Repository Citation

White, J. L., Doom, T. E., Wojcik, A. S., Chung, M., & Chisholm, G. (1997). Candidate Subcircuit Generation to Facilitate Identification of High-Level Components in Logic Circuits. .
https://corescholar.libraries.wright.edu/cse/291