Publication Date


Document Type


Committee Members

Andrew Hsu (Other), Marian Kazimierczuk (Committee Member), Saiyu Ren (Advisor), Raymond Siferd (Committee Member), Kefu Xue (Other)

Degree Name

Master of Science in Engineering (MSEgr)


In recent years, signal processing has gained ample significance making high speed and low voltage analog-to-digital converters (ADC) inevitable in numerous applications. Two such ADCs designed in CMOS 90nm technology are presented in this thesis.

In flash ADC, thermometer to binary encoder often becomes bottleneck in achieving high speed. An encoder deploying new CMOS logic, with fewer transistors through the use of pseudo-dynamic circuits is described. This 4 bit flash ADC operates at 5GHz with an average power dissipation of 1.3mW.

Folding and interpolation significantly reduces the number of comparators used in flash architecture. A 6 bit 400MSPS low power folding and interpolating ADC that has a power dissipation of 2.17mW is presented. Output synchronization circuit is not required as folding circuits are used in both fine and coarse converters. These can be used as building blocks in higher resolution pipeline ADC.

Page Count


Department or Program

Department of Electrical Engineering

Year Degree Awarded