Publication Date


Document Type


Committee Members

J.M. Emmert (Advisor), Saiyu Ren (Committee Member), Raymond Siferd (Committee Member)

Degree Name

Master of Science in Engineering (MSEgr)


As fabrication technologies improve logic densities increase. It becomes harder to mitigate clock skew and jitter. Higher clock rates combined with increased numbers of sinks increase mixed-system substrate noise. An increasingly popular approach to address these problems is clockless logic. One technique is Null Convention Logic (NCL). However, traditional NCL feedback loops have large area overhead and require many gate delays. This makes NCL impractical in many applications. In this paper we propose to replace the feedback logic with a two-stage voltage divider. Using our technique we show up to 50% area reduction and require only one unit gate delay.

Page Count


Department or Program

Department of Electrical Engineering

Year Degree Awarded