Publication Date
2015
Document Type
Thesis
Committee Members
Chien-in Henry Chen (Advisor), Marian Kazimierczuk (Committee Member), Yan Zhuang (Committee Member)
Degree Name
Master of Science in Engineering (MSEgr)
Abstract
The scaling down of IC's based on CMOS technology faces significant challenges due to technology advancing factors. The stand-by power becomes comparable to active power due to the increasing leakage current. Power gating and various low-power schemes have been proposed in the past to reduce the stand-by power in CMOS designs. As most random access memory (RAM) used for primary storage in personal computers is volatile memory, which needs constant voltage (power on) to store the data and results in a higher stand-by power. Magnetic Tunnel Junctions (MTJ) transistor has feature of non-volatility, endurance and high density, which makes it possible for next-generation logic and memory chips that do not need to have its memory content periodically refreshed. This thesis discusses design and performance analysis of magnetic logic gates, adders and memories using MTJs. Ultra-low stand-by power and dynamic power are observed and presented using MTJs.
Page Count
67
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2015
Copyright
Copyright 2015, all rights reserved. This open access ETD is published by Wright State University and OhioLINK.
