Publication Date
2016
Document Type
Thesis
Committee Members
Nikolaos Bourbakis (Committee Member), Soon Chung (Advisor), Yong Pei (Committee Member)
Degree Name
Master of Science in Computer Engineering (MSCE)
Abstract
Cache memory plays a vital role in a system's performance by acting as a buffer to quickly supply requested instruction/data blocks from the main memory to the central processing unit (CPU). Cache management techniques may increase or decrease a system's performance. The results vary from process to process, depending on how well optimized the cache management technique is for a particular process. The inclusion of level-2 (L2) cache locking has been shown in previous studies to be beneficial in increasing a system's performance. This is further improved upon through the inclusion of a miss table (MT), which keeps track of how often each block is missed in the L2 cache. In this research, we propose the use multiple MTs to keep track of the number of times each block is missed in the L2 cache during the run-time of a process. The information obtained from the multiple MTs are then used to lock the most missed blocks into the L2 cache. This is done by dividing the L2 cache into two partitions: a normal partition and a locked partition. The utilization of this cache memory management technique will aid in the reduction of cache misses.
Page Count
45
Department or Program
Department of Computer Science and Engineering
Year Degree Awarded
2016
Copyright
Copyright 2016, all rights reserved. My ETD will be available under the "Fair Use" terms of copyright law.
