Publication Date


Document Type


Committee Members

Chien-In Henry Chen (Advisor), Marty Emmert (Committee Member), Wen-Ben Jones (Committee Member), Marian Kazimierczuk (Committee Member), Saiyu Ren (Committee Member)

Degree Name

Doctor of Philosophy (PhD)


Chirp signals can achieve a high range resolution without sacrificing SNR or maximum range, making them a strong candidate for use in radar and sonar applications. Chirp signals are also power efficient and resistant to interference, making them well suited for communication applications as well. The proposed digital high chirp rate receivers will showcase the use of digital instantaneous frequency measurement (IFM) devices for high chirp rate measurement. The receivers are paired with a high resolution time-of-arrival algorithm, capable of detecting the TOA and TOD of a pulse with an average error of less than 2ns. The high resolution pulse detector is vital for the measurement of high chirp rate, short pulse duration chirp signals when no a priori knowledge of the signals or operating environment is available. Three different receivers were designed and implemented in order to target three different applications: linear chirp signals, nonlinear chirp signals, and linear chirp signals with varying pulse widths. In addition to the digital IFM and TOA algorithm, a high rate 43-tap Hilbert Transform was implemented via an FIR filter in order to convert incoming real data from the ADC into its complex signal representation. All three designs were synthesized and successfully tested on a Xilinx Virtex 6 SX475 FPGA which is paired with a Calypso 12-bit ADC sampling at 2.56GHz. All three receivers run at a rate of 320MHz and can measure chirp rates up to 1180MHz in 400ns. The designs boast an overall detection rate of greater than 97% with a false alarm rate of 10^-7 and achieve a frequency measurement error of less than 1% for both chirp rates and carrier frequencies. The receivers can successfully detect and measure chirp signals and stationary carrier frequencies with SNRs 5dB and higher. The largest design, the digital nonlinear chirp receiver only utilizes 13% of the Virtex 6 SX475 FPGA board.

Page Count


Department or Program

Ph.D. in Engineering

Year Degree Awarded


Included in

Engineering Commons