Publication Date
2019
Document Type
Thesis
Committee Members
John M. Emmert (Committee Chair), Michael Raymer (Committee Co-Chair), Travis Doom (Committee Member)
Degree Name
Master of Science in Cyber Security (M.S.C.S.)
Abstract
In recent decades, field programmable gate arrays (FPGAs) have evolved beyond simple, expensive computational components with minimal computing power to complex, inexpensive computational engines. Today, FPGAs can perform algorithmically complex problems with improved performance compared to sequential CPUs by taking advantage of parallelization. This concept can be readily applied to the computationally dense field of image manipulation and analysis. Processed on a standard CPU, image manipulation suffers with large image sets processed by highly sequential algorithms, but by carefully adhering to data dependencies, parallelized FPGA functions or kernels offer the possibility of significant improvement through threaded CPU functions. This thesis will examine the possibilities of moving a program featuring several image manipulation and analysis operations to a hardware/software build on a modern FPGA. The paper will focus on the implementation and performance improvements of the proposed method as well as the results of moving portions of the program to FPGA hardware.
Page Count
69
Department or Program
Department of Computer Science and Engineering
Year Degree Awarded
2019
Copyright
Copyright 2019, some rights reserved. My ETD may be copied and distributed only for non-commercial purposes and may not be modified. All use must give me credit as the original author.
Creative Commons License
This work is licensed under a Creative Commons Attribution-Noncommercial-No Derivative Works 3.0 License.
