Siferd Raymond (Advisor)
Doctor of Philosophy (PhD)
As the performance of integrated circuits (IC) improve, a more precise clock-signal is needed to regulate their actions. The primary objective of this dissertation is to improve the phase-lock loop (PLL), which is the most common type of clock-generator. A nonlinear phase-lock loop (NPLL) was developed by adding a nonlinear-gain unit to a standard PLL. The NPLL implementation improves performance compared to existing PLLs by demonstrating faster acquisition times and superior jitter performance. The nonlinear-gain is achieved by the use of a fuzzy controller. The fuzzy controller takes in a value and generates outputs based upon the rules that are programmed into it. The developed NPLL takes a 62.5 MHz off-chip clock-signal and generates a 2GHz on chip clock.
To demonstrate and confirm the viability of this approach, a clock-distribution system was designed based on the NPLL. The clock-distribution system is a global-shielded H-tree, coupled with a regional gird system. The NPLL and the clock-distribution system were designed using a IBM 130nm CMOS process.
The maximum jitter values that are achieved are as low as 2.6ps. The NPLL locks onto its input signal in approximately 200ns while consuming 1.98mW of power in an area of 133.9μm by 60.9μm. The clock-distribution system, supplies a low jitter clock signal to a chip area of 81mm2.
Department or Program
Ph.D. in Engineering
Year Degree Awarded
Copyright 2008, all rights reserved. This open access ETD is published by Wright State University and OhioLINK.