Broad Bandwidth High Resolution Analog to Digital Converters: Theory, Architecture and Implementation
Henry Chen (Committee Member), Marty Emmert (Committee Member), Marian Kazimierczuk (Committee Member), Frank Scarpino (Committee Member), Raymond Siferd (Advisor)
Doctor of Philosophy (PhD)
Analog to digital converters (ADCs) translate analog quantities, which are characteristic of most phenomena in the "real world" to digital language for a variety of applications including information processing, computing, communication and control systems. The performance of the digital signal processing and communication systems is generally limited by the speed and precision of the digital input signal which is achieved at the interface between analog and digital information. The analog to digital converter (ADC) has become a critical component for advanced telecommunication systems. The desire to move the analog to digital interface closer to the sensor has resulted in more stringent performance requirements for high speed, and high resolution ADCs. High speed ADCs have become the bottle neck for achieving high performance signal processing systems. This has motivated many researchers and scientists to continuously work on the development of innovative ADC architectures and new techniques. The dissertation is going to present 1) The design, fabrication and testing for a CMOS ADC architecture which has up to 62.5 MHz base bandwidth and 1 GHz sample frequency with 12 bits resolution. This work is done by using a unique patented architecture, "Pipelined Delta Sigma Modulator Analog to Digital Converter". 2) A CMOS band pass ADC which includes M single channel sub-sampling delta sigma modulators having N-bit quantizer outputs arranged in a time interleaved configuration. This unique patented architecture facilitates a flexible RF/IF Band Pass ADC. MATLAB SIMULINK simulation results show that more than 8 bits of resolution are obtained for center frequencies in the 1.8 GHz to 3.0 GHz region with a bandwidth of 70 MHz using time interleaved first order delta sigma modulators operating with sampling frequencies of 600 MHz to 1.0 GHz. 3) The design, fabrication and testing for CMOS Phase Lock Loop synthesizer architectures which will be able to generate In phase and Quadrature clock signals up to 7.8GHz frequency which may be used as the ADCs and receivers on chip clock source.
Department or Program
Ph.D. in Engineering
Year Degree Awarded
Copyright 2008, all rights reserved. This open access ETD is published by Wright State University and OhioLINK.