Hardware Security and Side Channel Power Analysis for 16X16 Booth Multiplier in 65nm CMOS Technology
Publication Date
2021
Document Type
Thesis
Committee Members
Saiyu Ren, Ph.D. (Advisor); Ray Siferd, Ph.D. (Committee Member); Marian K. Kazimierczuk, Ph.D. (Committee Member)
Degree Name
Master of Science in Electrical Engineering (MSEE)
Abstract
As feature size is scaling down, dynamic power consumption reduces but static power consumption increases. Due to the increase of static power, leakage currents as a source, the information can be exploited successfully as a side-channel to recover the secrets of the cryptographic implementations. An attacker who has access to the hardware fabrication can insert a Trojan to the design to steal or alter information. In this thesis, a post-fab static voltage variation/detection technique is developed to detect the potential fabrication process Trojan insertion. The technique is, dividing the designed circuit into N equal segments, where each segment would have same leakage current under certain input patterns. One-ohm resistor is embedded between each segment network to ground path to convert leakage current to voltage. Voltage drop on the one-ohm resistor is measured post-fab to identify the authentic of the design mathematically and statistically by comparing all the segment measure data. 250 Monte Carlo simulation results show that the minimum Trojan is 0.0868% of the host circuit size with 100% detection probability.
Page Count
74
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2021
Copyright
Copyright 2021, some rights reserved. My ETD may be copied and distributed only for non-commercial purposes and may not be modified. All use must give me credit as the original author.
Creative Commons License
This work is licensed under a Creative Commons Attribution-Noncommercial-No Derivative Works 3.0 License.
