Marty Emmert (Advisor), Saiyu Ren (Committee Member), Raymond Siferd (Committee Member)
Master of Science in Engineering (MSEgr)
In this work we present the design and characterization of a parameterizable Digital Single Sideband Modulator (DSSM) circuit for use with a Digital Radio Frequency Memory (DRFM) or other signal processing circuits. Field Programmable Gate Arrays (FPGAs) can be used as a prototyping platform for quickly verifying and hardware testing a digital circuit or system. FPGAs can also be used as an implementation platform for a digital circuit or system. A main advantage of FPGAs over that of an Application Specific Integrated Circuit (ASIC) is that it can be quickly (and often dynamically) reprogrammed; whereas an ASIC can take months to fabricate.
Currently there is limited capability to quickly and easily generate backend digital signal processing systems for electronic warfare (EW) applications for implementation on an FPGA or an ASIC platform. It is advantageous (especially for dynamically reprogramming FPGAs) for backend EW processing to have parameterizable hardware description language (HDL) code to assist in quickly implementing digital processing capabilities for EW systems. The purpose of this thesis work is to provide just such a capability. We present a completely generic VHDL digital single sideband modulator (DSSM) based on a parameterizable Hilbert Transform (HT). We characterize and test the code so that the user can quickly implement a system to meet their expectations. The entire system is described in VHDL to provide an inexpensive, long term, portable, and parameterizable solution which allows for rapid design and redesign of DSSM circuits. This design is technology portable so it will be viable now and in the future for rapid prototyping, demonstration, and implementation. So as technology changes this code transitions with it. The DSSM via HT rapidly delivers digital circuits for FPGA or ASIC radar or other EW applications.
Department or Program
Department of Electrical Engineering
Year Degree Awarded
Copyright 2010, all rights reserved. This open access ETD is published by Wright State University and OhioLINK.