John Emmert (Committee Member), Marian Kazimierczuk (Committee Member), Raymond Siferd (Advisor)
Master of Science in Engineering (MSEgr)
A 2GHz carrier recovery Costas Loop based BPSK detector is designed using CMOS 0.18μm technology. The designed BPSK detector consists of single to differential conversion circuit, phase/frequency detector, Voltage Controlled Oscillator, differential to single conversion circuit, first order loop filter and a third multiplier. Different architectures available for each block have been discussed along with the design methodology adopted. The schematics were simulated in analog design environment.
The Costas loop presented in this work can sense both 0° and 180° phases at its input. Thus the Costas loop carrier recovery circuit overcomes the 180° phase ambiguity presented by the conventional PLL. The designed Costas loop for BPSK detection is able to detect and demodulate data rates up to 50Mbps. The loop can track with in the VCO frequency range of 1.99GHz to 2.01GHz. The lock range achieved for this loop is 20MHz. The power consumption of the Costas Loop BPSK detector was found to be 144mw.
Department or Program
Department of Electrical Engineering
Year Degree Awarded
Copyright 2008, all rights reserved. This open access ETD is published by Wright State University and OhioLINK.