The design of a VLSI circuit consists of a description of the circuit in terms of its components and subcomponents, at various levels of detail. To verify that the layout of a VLSI circuit conforms to its design, one needs to work backwards from the lowest-level description of the circuit and recognize the higher-level components it constitutes. This paper is concerned with the application of logic programming techniques in the formal verification of the structural correctness of the VLSI circuit layouts. In particular, we review Michael Dukes' Generalized Extraction System (1990) that compiles design descriptions into a set of extraction rules, and then study the benefits and the limitations of using a meta-interpreter approach to extraction.
(1995). A Meta-Interpreter for Circuit-Extraction. Proceedings of the IEEE 1995 National Aerospace and Electronics Conference, 2, 680-684.