Suppressed Gate Current in a Superlattice-Insulated-Gate Field-Effect Transistor on InP
Document Type
Article
Publication Date
1-1-1995
Identifier/URL
43037384 (Pure)
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Abstract
A new insulating layer is used in a normally-off (i.e., enhancement-mode) field-effect transistor on an InP substrate. It consists of closely spaced, strained AlAs barriers embedded in In0.52Al0.48As between the In0.53Al0.47As channel and the metal gate. This insulating layer increases the forward-bias gate turn-on voltage by approximately 50% and reduces the gate leakage current by as much as 50 times compared to a conventional In0.52Al0.48As insulating layer. In addition, the transistor characteristics are significantly improved such that the maximum current is increased approximately three times and the peak transconductance is increased by 70%. These properties are explained by superior confinement of electrons to the channel in the presence of the AlAs barriers.
Repository Citation
Brown, E. R.,
Chen, C. L.,
Mahoney, L. J.,
Maki, P. A.,
& Nichols, K. B.
(1995). Suppressed Gate Current in a Superlattice-Insulated-Gate Field-Effect Transistor on InP. Applied Physics Letters, 66 (18), 2352-2354.
https://corescholar.libraries.wright.edu/physics/1401
DOI
10.1063/1.113980
