Copper Electroplating Approaches for 16nm Technology

Document Type

Article

Publication Date

5-1-2010

Abstract

Electrodeposition processes have evolved to achieve increasingly fast bottom-up copper growth in the features, as well as high nucleation densities that protect the thinnest areas of copper seed as the plating process begins [1-3] to take advantage of the improved seed layers in smaller features. This combination of PVD and electroplating has already been extended to fill feature dimensions beyond what was believed possible several years ago, and efforts are now directed toward development of processes capable of filling 1X nm memory structures and 16nm logic interconnects.


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