Publication Date
2011
Document Type
Thesis
Committee Members
Henry Chen (Committee Member), Saiyu Ren (Advisor), Raymond Siferd (Committee Member)
Degree Name
Master of Science in Engineering (MSEgr)
Abstract
This thesis presents a high-frequency wide tuning range all digital phase locked loop (ADPLL) in 90 nm CMOS process with 1.2 V power supply. It operates in the frequency range of 2-7.2 GHz with wide linearity and high resolution. The ADPLL uses a wide frequency range digital controlled oscillator (DCO) and averaging technique to obtain fast lock time. The operation of the ADPLL includes both a frequency acquisition state and a phase acquisition state. A novel architecture is implemented in a coarse stage to obtain a monotonically increasing wide frequency range DCO for frequency acquisition and a fine control stage is used to achieve resolution of 0.1 MHz for phase tracking and maintenance. Design considerations of the ADPLL circuit components and implementation using Cadence tools are presented. Spectre simulations demonstrate a significant improvement compared to recent architectures with 15 ps of peak-peak jitter and a root mean square value of 4 ps when locked at 5.12 GHz. The power consumption at 5.12 GHz is 5 mW and the locking time is 3.5 μs.
Page Count
71
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2011
Copyright
Copyright 2011, all rights reserved. This open access ETD is published by Wright State University and OhioLINK.
