Publication Date
2007
Document Type
Thesis
Committee Members
John Emmert (Advisor)
Degree Name
Master of Science in Engineering (MSEgr)
Abstract
Wideband digital receivers are important components used prevalently by the United States Air Force for many modern electronic warfare systems. Currently, many digital receiver architectures are designed for a specific mission requirement and are not parameterizable, modular, or reusable for varying mission requirements. Also, many designs are technology, platform, and vendor dependent which make upgrading existing fielded systems costly and difficult. Additionally, current wideband FFT-based digital receivers must wait until a number of samples equal to the size of the FFT are collected before spectral information can be updated. Achieving a high spectral update rate is important for the accurate detection of the time of arrival of radar pulses so that enemy signals can be detected and located quickly. Current methods to increase the effective spectral update rate by N require an N-fold increase in clock rate or an N-fold increase in area. For this research, a parameterizable channelized wideband digital receiver architecture is proposed that takes advantage of the tradeoffs between frequency resolution and spectral update rate while preserving bandwidth, reducing hardware requirements, and increasing throughput. The design is completely parameterizable to suit varying mission requirements, and it has been written in generic VHDL which was targeted toward FPGA and ASIC platforms with no code modification. Components developed in VHDL include the decimation filter and Parks-McClellan filter design algorithm. The FPGA implementation was fully tested, and for the parameters chosen, was able to achieve an 8x improvement in update rate.
Page Count
135
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2007
Copyright
Copyright 2007, all rights reserved. This open access ETD is published by Wright State University and OhioLINK.
