Publication Date
2015
Document Type
Thesis
Committee Members
John Emmert (Committee Member), Saiyu Ren (Advisor), Arnab Shaw (Committee Member), Raymond Siferd (Committee Member)
Degree Name
Master of Science in Engineering (MSEgr)
Abstract
An analog automatic gain control circuit (AGC) and mixer were implemented in 130 nm CMOS technology. The proposed AGC was intended for implementation into a wireless receiver chain. Design specifications required a 60 dB tuning range on the output of the AGC, a settling time within several microseconds, and minimum circuit complexity to reduce area usage and power consumption.
Desired AGC functionality was achieved through the use of four nonlinear variable gain amplifiers (VGAs) and a single LC filter in the forward path of the circuit and a control loop containing an RMS power detector, a multistage comparator, and a charging capacitor. Down conversion of the AGC output signal to a low frequency was achieved through the use of a modified quadrature Gilbert cell mixer.
The proposed AGC achieves a 63 dB practical tuning range with a settling time of 2 µs for the worst case input condition. Estimated power consumption of the circuit is 4.41 mW when operating at maximum gain. The proposed AGC suppresses DC offset corruption introduced from the mixer and minimizes undesirable variations in the steady-state response.
Page Count
90
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2015
Copyright
Copyright 2015, some rights reserved. My ETD may be copied and distributed only for non-commercial purposes and may not be modified. All use must give me credit as the original author.
Creative Commons License
This work is licensed under a Creative Commons Attribution-Noncommercial-No Derivative Works 3.0 License.
