Publication Date
2016
Document Type
Thesis
Committee Members
John Marty Emmert (Advisor), Saiyu Ren (Committee Member), Raymond Siferd (Committee Member)
Degree Name
Master of Science in Electrical Engineering (MSEE)
Abstract
Relative to integrated circuit (IC) systems, on-chip fault detection entails determi- nation of whether or not a fault exists. The cause of the fault could be some faulty logic resource or some faulty interconnect (wiring) resource, but typically, fault detection only determines if a fault exists, not what exactly is faulty. Beyond pure fault detection some work has been done relative to on-chip fault analysis to fur- ther determine not only if a fault exists, but exactly what is faulty. Even less work has been done to actually tolerate faulty resources once they have been found. For this work, we take advantage of previous work (ROVING STARS) that detects on-chip faults and analyzes those faults to determine exactly what is faulty. We developed, tested and demonstrated an on-chip technique that takes advantage of dynamic partially reconfigurable field programmable gate arrays (FPGAs) to automatically reconfigure the FPGA for tolerating logic faults.
Page Count
52
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2016
Copyright
Copyright 2016, some rights reserved. My ETD may be copied and distributed only for non-commercial purposes and may be modified only if the modified version is distributed with these same permissions. All use must give me credit as the original author.
Creative Commons License
This work is licensed under a Creative Commons Attribution-Noncommercial-Share Alike 3.0 License.
