Publication Date
2017
Document Type
Thesis
Committee Members
Saiyu Ren (Advisor), Ray Siferd (Committee Member), Jiafeng Xie (Committee Member)
Degree Name
Master of Science in Electrical Engineering (MSEE)
Abstract
According to Moore’s law, number of transistors integrated on a single chip double every 18 months with a lot new functionality embedded, which results the increasing of delay and power consumption of a chip. To improve the performance of a more complicated digital circuit design, faster and power efficient digital sub-components are in urgent need. Multipliers are the key components in the field of DSP, GPU and CPU which compute enormous amount of binary data. A radix-4 8*8 booth multiplier is proposed and implemented in this thesis aiming to reduce power delay product. Four stages with different architecture are used to implement this multiplier rather than traditional 8*8 booth multiplier. Instead of using adder in stage-1, it is replaced with binary-to-access one converter circuit and 10-bit MUX 2:1 to reduce power consumption by 23.76% and increase speed by 12.02% compared to stage-1 of traditional 8*8 booth multiplier. This proposed design is implemented in CMOS 32nm technology at 1.0 voltage supply. The worst-case delay of the proposed radix-4 8*8 booth multiplier at 2 Giga data rate is 423 picosecond and power consumption of 0.274 milli-watts with transistor count of 2860.
Page Count
67
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2017
Copyright
Copyright 2017, all rights reserved. My ETD will be available under the "Fair Use" terms of copyright law.
