Publication Date
2017
Document Type
Thesis
Committee Members
Chien-In Henry Chen (Advisor), Jiafeng Xie (Committee Member), Yan Zhuang (Committee Member)
Degree Name
Master of Science in Electrical Engineering (MSEE)
Abstract
SRAMs are widely used in application based systems like medical instruments, portable electronic devices from caches to registers. Technology scaling of transistor into nanometer regime has substantially increased memory density that occupies large silicon area in today's IC's and consumes significant amount of active and leakage power. So, design requirements and challenges such as memory write and read speed, leakage power, noise margin and process-voltage-temperature (PVT) variations also significantly increase. In this thesis, a 13T single-ended low power SRAM using Schmitt-Trigger and write-assist technique is presented. It enhances read static noise margin, write-1 and read-0 access time, specifically at low supply voltages. Designed in 1.05V 32 nanometer CMOS process, employing a Schmitt-Trigger in SRAM design achieves a higher read static noise margin (RSNM) of 3.65x and 1.79x as that of the standard 6T and conventional 8T SRAM, respectively. The read port configuration used in this SRAM design reduces about 50% of the Read-Bit-Line (RBL) leakage from un-accessed memory cells as compared with conventional 8T SRAM. The SRAM functions successfully with a minimum VDD of 340 mV, 100 mV lower than the threshold voltage so as to consume extremely low power.
Page Count
55
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2017
Copyright
Copyright 2017, some rights reserved. My ETD may be copied and distributed only for non-commercial purposes and may not be modified. All use must give me credit as the original author.
Creative Commons License
This work is licensed under a Creative Commons Attribution-Noncommercial-No Derivative Works 3.0 License.
