Publication Date
2017
Document Type
Thesis
Committee Members
Marian K. Kazimierczuk (Committee Member), Saiyu Ren (Advisor), Raymond E. Siferd (Committee Member), Yan Zhuang (Committee Member)
Degree Name
Master of Science in Electrical Engineering (MSEE)
Abstract
Digital-to-analog converters are the interface circuits between digital and analog domains. They are used in data communication applications and different sorts of applications where transformation amongst digital and analog signals is needed. High-speed data converters are needed to match the bandwidth demands of the present-day communication systems. This thesis presents the layout implementation of a 10-bit current steering DAC with a sampling rate of about 1.2 GS/s using CMOS 90 nm technology. Current steering DAC topology is used in high-speed applications. The DAC in this thesis is designed using a segmented architecture in which 4 LSB current cells are binary weighted and 6 MSB current cells are thermometer encoded. The issues with the mixed signal layout were discussed. The schematic design does not consider the effect of parasitic resistance and capacitance whereas the layout does. The performance of the schematic and layout designs of the sub-circuits was compared. Post layout simulations of the implemented current steering DAC were performed in Cadence with 1.2 GHz clock and 55.07 MHz input signal. The simulations show that the DAC is functional and comparisons between the layout and schematic were presented.
Page Count
72
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2017
Copyright
Copyright 2017, all rights reserved. My ETD will be available under the "Fair Use" terms of copyright law.
