Publication Date
2006
Document Type
Thesis
Committee Members
Raymond Siferd (Advisor)
Degree Name
Master of Science in Engineering (MSEgr)
Abstract
This thesis proposes the use of a Systolic Array of Multi-Rate FIR Filters to improve performance by eliminating the requirement of the FFT and De-Multiplexer associated with the conventional receiver while achieving the same functionality. The FFT is a major bottle neck for improving system performance for the conventional DCWBR because many complex multiplications and additions are required. The proposed new architecture is designed and evaluated in MATLAB to illustrate its viability. Two approaches for improved channel arbitration are accessed in MATLAB, namely, channel bin’s rms comparison and parallelism of the Systolic Array Multi-Rate FIR Filters. The FIR filters (high-pass & low-pass) were successfully designed with Cadence tools using 0.13um technology and are fully functional at clock frequencies up to 1.8 GHz. The limitation of computing resources/verification tools prevented the simulation of the entire array of Multi-Rate filters as proposed. Nevertheless, a two tier tree of Multi-Rate FIR filters demonstrated channelization in cadence (simulations which can be completed within the constraints of computing facilities) and is consistent with those of MATLAB; thus, proving the viability of using the Systolic Array of Multi-Rate FIR Filters as a potential architecture for improving performance of DCWBR.
Page Count
123
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2006
Copyright
Copyright 2006, all rights reserved. This open access ETD is published by Wright State University and OhioLINK.
