Publication Date
2021
Document Type
Dissertation
Committee Members
Marian Kazimierczuk, Ph.D., D. Sci. (Advisor); Michael Schuette, Ph.D. (Committee Member); Yan Zhuang, Ph.D. (Committee Member); Saiyu Ren, Ph.D. (Committee Member); Ray Siferd, Ph.D. (Committee Member)
Degree Name
Doctor of Philosophy (PhD)
Abstract
Amorphous and nano-crystalline metal oxide semiconductors are an important class of materials under continuing investigation for emerging technologies. Accurate measurements of electron mobility in these materials is critical for furthering overall device development. This is complicated due to the fact that device measurements such as current response, transistor input and output characteristics, as well as mobility are affected by transport-limiting factors, such as charge trapping effects at the dielectric / active layer interface, and restriction of electronic transport across grain boundaries. In this work, we focus on the binary metal oxide thin film transistor (ZnO TFT), a normally-off (e-mode) transistor with a positive threshold voltage (Vth) and a large ( > 10 MΩ)) sheet resistance at gate voltage below threshold (VG < Vth), Field-effect and Hall (extrinsic and intrinsic mobilities) were measured on the same device at the same time (concurrent mobility measurements of our gated Hall system) at device relevant dimensions (25 nm Al2O3, gate dielectric, 50 nm ZnO active layer), at typical transistor gate and drain bias device operating conditions (VG < 10 V and VD biased in the linear region), on the same device (100 × 100 µm Van der Pauw). The large sheet resistance (RS) of the material requires electrostatic doping (by gate bias) in order to modulate resistance and increase Hall test current. However, as VG interacts with VD and VS, resulting vertical electric fields EGS and EGD must remain below dielectric breakdown (EBD). The result of meeting these test requirements led to a fully automated gated Hall test system capable of making measurements and comparisons of mobility across the allowable test bias spectrum (VG and VD). A design of experiment in which test wafers were compared between in situ deposition and exposure to clean room ambient air between the dielectric and active layer depositions (by atomic layer deposition) was used to examine interface effects. Post temperature oven annealing was used to compare differences in grain boundary effects by increasing grain size. A simple model of two transport regimes was developed (localized and non-localized transport) to fit several contradictory trends observed in the measured data sets.
Page Count
124
Department or Program
Engineering PhD
Year Degree Awarded
2021
Copyright
Copyright 2021, all rights reserved. My ETD will be available under the "Fair Use" terms of copyright law.
ORCID ID
0000-0001-9930-7456
