Publication Date
2022
Document Type
Dissertation
Committee Members
Travis E. Doom, Ph.D. (Advisor); Jack S. N. Jean, Ph.D. (Committee Member); Michael L. Raymer, Ph.D. (Committee Member); Krishnaprasad Thirunarayan, Ph.D. (Committee Member); Vincent A. Schmidt, Ph.D. (Committee Member); Thomas Wischgoll, Ph.D. (Other); Shu Schiller, Ph.D. (Other)
Degree Name
Doctor of Philosophy (PhD)
Abstract
This research is about securing control of those devices we most depend on for integrity and confidentiality. An emerging concern is that complex integrated circuits may be subject to exploitable defects or backdoors, and measures for inspection and audit of these chips are neither supported nor scalable. One approach for providing a “supply chain firewall” may be to forgo such components, and instead to build central processing units (CPUs) and other complex logic from simple, generic parts. This work investigates the capability and speed ceiling when open-source hardware methodologies are fused with maker-scale assembly tools and visible-scale final inspection.
The author has designed, and demonstrated in simulation, a 36-bit CPU and protected memory subsystem that use only synchronous static random access memory (SRAM) and trivial glue logic integrated circuits as components. The design presently lacks preemptive multitasking, ability to load firmware into the SRAMs used as logic elements, and input/output. Strategies are presented for adding these missing subsystems, again using only SRAM and trivial glue logic. A load-store architecture is employed with four clock cycles per instruction. Simulations indicate that a clock speed of at least 64 MHz is probable, corresponding to 16 million instructions per second (16 MIPS), despite the architecture containing no microprocessors, field programmable gate arrays, programmable logic devices, application specific integrated circuits, or other purchased complex logic.
The lower speed, larger size, higher power consumption, and higher cost of an “SRAM minicomputer,” compared to traditional microcontrollers, may be offset by the fully open architecture—hardware and firmware—along with more rigorous user control, reliability, transparency, and auditability of the system. SRAM logic is also particularly well suited for building arithmetic logic units, and can implement complex operations such as population count, a hash function for associative arrays, or a pseudorandom number generator with good statistical properties in as few as eight clock cycles per 36-bit word processed. 36-bit unsigned multiplication can be implemented in software in 47 instructions or fewer (188 clock cycles). A general theory is developed for fast SRAM parallel multipliers should they be needed.
All tools and work product of this research are available online with open-source licenses.
Page Count
460
Department or Program
Department of Computer Science and Engineering
Year Degree Awarded
2022
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 International License.
ORCID ID
0000-0003-4020-0544
