Publication Date
2016
Document Type
Dissertation
Committee Members
Marian Kazimierczuk, Ph.D. (Advisor); Henry Chen, Ph.D. (Committee Member); Gregory Kozlowski, Ph.D. (Committee Member); Ronald Coutu, Ph.D. (Committee Member); Brad Bryant, Ph.D. (Committee Member)
Degree Name
Doctor of Philosophy (PhD)
Abstract
Today many consumer, industrial, and military electronic systems are digital in nature and are utilized for multiple applications. Many of these systems were designed to be portable and generally have limited capabilities because of size, weight, and power requirements. The last several decades have seen the push for more power efficient electronics. Thus, researchers and scientists investigated advanced process technologies and more power efficient circuit implementations. This research is concerned with classes of applications intended to operate over long periods of time with a low duty cycle, but are subject to bursts of information, requiring high processing capabilities. Specifically, this research focused on the development of an adaptive power digital interface suitable for remote sensor applications. These applications generally are equipped with an analog sensor that must be converted into a digital format for further processing. An analog-to-digital interface architecture with support for dynamically switching subsequent processing circuitry between performance, low power, and subthreshold modes was developed. This dissertation presents: 1. An understanding of CMOS operation across dynamic power modes is described. The intended applications require sensor systems to operate for extended periods of time with very low power consumption. It is feasible to operate such circuits in the subthreshold region, but certain tradeoffs are required to allow operation in the superthreshold region for performance. This work investigated potential tradeoffs to facilitate the development of supporting control circuitry. 2. Development of the Current Monitoring and Drive Compensation (CMDC) concept was undertaken as part of this work. CMDC allows the circuitry (i.e. processing, logic, storage) to be dynamically switched between performance and power modes. SPICE level simulations have shown that the architecture is feasible and can support operation across different modes. 3. The design, simulation, and verification of an adaptive power analog-to-digital interface (APADI) completed as part of this work. The architecture supports tradeoffs between resolution, sampling rate, and power to achieve low aggregate power consumption. Circuit designs were developed using a mixed-signal 180 nm CMOS process technology and schematically captured using the Silvaco design environment for analog, mixed-signal, and RF circuit design, simulation, and verification.
Page Count
220
Department or Program
Ph.D. in Engineering
Year Degree Awarded
2016
Copyright
Copyright 2016, all rights reserved. My ETD will be available under the "Fair Use" terms of copyright law.
ORCID ID
0000-0002-1949-2944
