Publication Date
2018
Document Type
Thesis
Committee Members
Marian Kazimierczuk, Ph.D. (Advisor); Ray Siferd, Ph.D. (Committee Member); LaVern Starman, Ph.D. (Committee Member)
Degree Name
Master of Science in Electrical Engineering (MSEE)
Abstract
Advancements in Direct Current (DC) electrical power systems have enabled new functionality in many, varied applications. Discrete power semiconductor devices are increasing in efficiency, switching frequency, and power density, resulting in greater usage of DC power management and distribution methods, including DC/DC conversion. DC distribution lacks inherent capability to safely and effectively break fault current, particularly in mobile solutions, where larger and slower electromechanical switching devices are not optimal or feasible. One solution is to design a low-energy breaking point into a switching power supply. Simpler converter designs, with a lower number of switching devices, have been modeled and can be functionally utilized for this purpose. However, these designs cannot easily or efficiently provide isolation between the source and the load. A full-bridge DC/DC converter can accomplish this task with galvanic isolation through a transformer. The full-bridge DC/DC converter is fairly complex to analyze with state-space analysis and does not have an existing averaged model. This thesis focuses on developing averaged and small-signal models for the full-bridge DC/DC converter; validating the small-signal averaged models by simulation in SABER circuit simulation software; and using the validated models to design a full-bridge DC/DC converter for simulation in SABER. The converter power stage is designed along with a Type II controller, a comparative current limit, non-Zero-Voltage-Switching gate drives, and a synchronous rectifier. The designed converter is evaluated for closed-loop stability against step changes in input voltage, load current, and reference voltage. The results are provided to show sufficient response of the full-bridge DC/DC converter, given the design parameters. The proposed architecture accommodates future work to reduce DC fault let-through energy.
Page Count
76
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2018
Copyright
Copyright 2018, all rights reserved. My ETD will be available under the "Fair Use" terms of copyright law.
