Publication Date
2006
Document Type
Thesis
Committee Members
Raymond Siferd (Advisor)
Degree Name
Master of Science in Engineering (MSEgr)
Abstract
The direct digital synthesizer is a method of signal generation with many benefits. DDS designs are able to switch frequencies very quickly and also tune precisely to many different frequencies with the use of a constant operating frequency. There is a need for a low power, high speed DDS in the form an ASIC design. One major bottleneck in common DDS systems is the slow access time of a ROM. There is also a need for a high speed ROM alternative. This thesis delivers a high speed ASIC Direct Digital Synthesizer which operates at a 1 GHz operating frequency. This high speed DDS design also operated with the low power consumption of fewer than 60 mW. As the results indicate this thesis delivers a possible solution to all of the stated design needs. This implementation could be used by any design that requires an ASIC generated sine wave as an input. This design also implements a unique alternative to the well known ROM bottleneck. This alternative performed at a high operating frequency and also allows for the addition of a pipeline stage, if an even higher operating frequency was desired. Any ASIC design that requires fast frequency hopping could utilize this implementation as well. This design was able to switch frequencies in fewer than 6 ns at the 1 GHz operating frequency. The frequencies this design was able to output ranged between 976.563 kHz and 249.023 MHz.
Page Count
108
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2006
Copyright
Copyright 2006, all rights reserved. This open access ETD is published by Wright State University and OhioLINK.
