Publication Date
2011
Document Type
Thesis
Committee Members
Stephen Hary (Committee Member), Saiyu Ren (Advisor), Raymond Siferd (Committee Member)
Degree Name
Master of Science in Engineering (MSEgr)
Abstract
A digital down converter (DDC) typically receives a digital input that has been generated by an analog to digital converter (ADC) operating at intermediate frequency (IF) in an RF receiver chain. The function of the DDC is to down convert the IF signal to baseband in phase (I) and quadrature (Q) signals and is a very important component in wireless receivers. A Digital Down Converter (DDC) is developed based on square wave local oscillators facilitating a multiplier-less implementation with no constraints on the sampling frequency. The DDC includes a pseudo multi-rate SINC low pass filter which exhibits better performance compared to the standard multi-stage SINC filter. The pseudo multi-rate SINC filter can be implemented with a unique cascaded integrator comb (CIC) filter to obtain the same improved performance. A 90nm CMOS design takes 8 bit inputs centered at 25 MHz with a bandwidth of 30 MHz and is clocked at 400MHz. The design demonstrates a flexible, very low power/size DDC architecture for single chip digital receiver applications. The layout area is 333.485um x 617.6um and the power consumption is 12.54mW when clocked at 400MHz.
Page Count
96
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2011
Copyright
Copyright 2011, all rights reserved. This open access ETD is published by Wright State University and OhioLINK.
