Publication Date
2011
Document Type
Thesis
Committee Members
Chien-in Henry Chen (Advisor), Jack Jean (Committee Member), Yan Zhuang (Committee Member)
Degree Name
Master of Science in Engineering (MSEgr)
Abstract
Dynamic CMOS circuits are used in microprocessors as well as in circuits that require high speed and small areas. Dynamic CMOS circuits have many advantages but are not robust in noise tolerance in comparison with the legacy static CMOS circuits. In this thesis several noise tolerance techniques that can be implemented with Dynamic CMOS circuits for robust noise tolerance are studied. A dynamic footed with clock overlapping technique integrated with a load balancing multiple-path transistor sizing algorithm for optimizing performance of noise tolerance and speed while in consideration of process variations is presented. Using the 2-bit weighted binary-to-thermometric converter implemented in 130-nanometer CMOS process as a benchmark circuit, noise tolerance and speed measurements were conducted by Monte-Carlo simulation in process variations. The input noise tolerance for the benchmark circuit was improved by 75%. The worst-case delay and standard deviation in process variations were improved by 52.2% and 53.5%, respectively.
Page Count
74
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2011
Copyright
Copyright 2011, all rights reserved. This open access ETD is published by Wright State University and OhioLINK.
