Publication Date
2013
Document Type
Thesis
Committee Members
R.William Ayres (Other), Chein-in Henry Chen (Committee Member), Saiyu Ren (Advisor), Raymond E. Siferd (Committee Member)
Degree Name
Master of Science in Engineering (MSEgr)
Abstract
A ROM-less direct digital synthesizer architecture is presented in this thesis. This architecture eliminates the ROM-based phase to sine wave amplitude converter, which is a bottleneck for pushing clock frequencies into the gigahertz range. The design consists of a 16-bit phase accumulator, a set of 18 band pass finite impulse response filters, a 12-bit digital to analog converter and a low pass filter to produce a sine wave with output frequencies ranging from 36 MHz to 72 MHz with a resolution of 3.05 kHz and a 55 dB spur free dynamic range. The same hardware can be used to achieve output frequency ranging from hertz to gigahertz and a 191 Hz resolution by changing the clock frequency. A resolution of 0.05 Hz can be achieved by using a 32-bit phase accumulator. The average phase noise obtained was -87 dBc/Hz at 100 kHz offset, -118 dBc/Hz at 1 MHz offset and -151 dBc/Hz at 5 MHz offset. This design was implemented on Virtex-6 FPGA. The analysis results of FPGA data show that the proposed design is an effective alternative. An ASIC design was also implemented in CMOS 90nm technology to reach higher frequency ranges.
Page Count
75
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2013
Copyright
Copyright 2013, all rights reserved. This open access ETD is published by Wright State University and OhioLINK.
