Publication Date
2013
Document Type
Thesis
Committee Members
Henry Chen (Advisor), Saiyu Ren (Committee Member), Yan Zhuang (Committee Member)
Degree Name
Master of Science in Engineering (MSEgr)
Abstract
An effective approach to timing and power optimization for single clocking and multiple clocking dynamic CMOS designs is presented in this thesis. For the single-clocking scheme dynamic CMOS sub-blocks can be replaced by static CMOS and mixed-dynamic-static CMOS for power minimization. For the multiple-clocking scheme the delay of data ready for use plays more important role than its clock pulse in timing optimization. Power minimization can be achieved by implementing dynamic CMOS sub-blocks with static or mixed-dynamic-static CMOS. In comparison with the benchmark 16-bit carry select adder in dynamic CMOS, the critical path delay is reduced by 41.1% using the single-clock optimization approach; the power and delay are reduced by 43% and 41.1% respectively using the multiple-clock optimization approach. In comparison with the benchmark 64-bit comparator in dynamic CMOS, the critical path delay is reduced by 49% using the single-clock optimization approach; the power and delay are reduced by 43.1% and 49% respectively using the multiple-clock optimization approach.
Page Count
60
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2013
Copyright
Copyright 2013, some rights reserved. My ETD may be copied and distributed only for non-commercial purposes and may not be modified. All use must give me credit as the original author.
Creative Commons License
This work is licensed under a Creative Commons Attribution-Noncommercial-No Derivative Works 3.0 License.
