Publication Date


Document Type


Committee Members

Henry Chen (Advisor), Marian K. Kazimierczuk (Committee Member), Yan Zhuang (Committee Member)

Degree Name

Master of Science in Engineering (MSEgr)


Two novel techniques, feedback inverter loop and pull-down bridge, adopted for multiple-input multiple-output (MIMO) dynamic CMOS circuits have been proposed in this thesis. The pull-down bridge technique optimizes the area and power of a single stage MIMO dynamic CMOS circuits, and the feedback inverter loop (FIL) technique improves the speed of multiple-stage dynamic CMOS circuits. Applying the pull-down bridge to the MIMO dynamic CMOS seven segment decoder, it is shown that common paths of different outputs are shared and optimized, which accounts for 12% speed improvement, 48% power reduction, and 73% area saving, as compared to the conventional logic design. Next, an optimized 64-bit binary comparator implemented by mixed-static-dynamic CMOS with FILs is presented. After partitioning the conventional dynamic CMOS into a mixed-static-dynamic CMOS, optimizing transistor sizes and using the FILs on the critical paths, the proposed design achieves 60% speed improvement and 42% power reduction, as compared to the conventional 64-bit dynamic CMOS comparator.

Page Count


Department or Program

Department of Electrical Engineering

Year Degree Awarded


Creative Commons License

Creative Commons Attribution-Noncommercial-No Derivative Works 3.0 License
This work is licensed under a Creative Commons Attribution-Noncommercial-No Derivative Works 3.0 License.