Publication Date
2008
Document Type
Thesis
Committee Members
Chien-in Henry Chen (Advisor), John M. Emmert (Committee Member), Raymond E. Siferd (Committee Member)
Degree Name
Master of Science in Engineering (MSEgr)
Abstract
Digital receivers involve fast Fourier transform (FFT) computations that require a large amount of arithmetic operations. The implementation of a FFT processor is one of the most challenging parts in the realization of a wideband receiver and its hardware complexity is very high. Hence, kernel function FFT processors have been proposed to meet real-time processing requirements and to reduce hardware complexity by rounding the kernel function to predetermined kernel points so as to eliminate the multipliers and use only shifters and adders or subtractors. Because of the nonlinear nature of this approximation by the rounding errors, spurious responses are generated and reduce the two signal instantaneous dynamic range (IDR) of the receiver in comparison with ideal FFT. Furthermore, there is a need to increase the resolution bits of the analog-to-digital converter (ADC) for FFT to improve the receiver performance by reducing the false alarm and increasing the spur-free dynamic range (SFDR).
In this research, architecture for an FPGA-based 2.56 giga sample per second (GSPS) fixed kernel function FFT, using a truncated 10-bit ADC, is implemented. The FFT can produce an averaged single signal SFDR using the ideal ADC, of 22.8 dB with the ability to produce a two-signal IDR using the ideal ADC with a performance of 20.8 dB. With the ADC utilizing the eight most significant bit (MSB) values, the FPGA-based FFT can detect a weak input signal at -17.6 dBm at a full scale amplitude of 3.6 dBm. The resulting spurious-free dynamic range (SFDR) has a performance of 21.2 dB, which is very close to the ideal realization. The eight least significant bit (LSB) values where evaluated as well, generating a low signal detection of -22.7 dBm for a full scale amplitude of -9.3 dBm. This truncation scheme resulted in an SFDR performance of 13.4 dB. There was also a reduction in the hardware utilization with the FPGA implementation. With the employment of a folding technique the available resources where reduces by over 50% in comparison with the unfolded models.
Page Count
85
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2008
Copyright
Copyright 2008, all rights reserved. This open access ETD is published by Wright State University and OhioLINK.
