Publication Date
2008
Document Type
Thesis
Committee Members
Henry Chen (Committee Member), Marty Emmert (Advisor), Ray Siferd (Committee Member)
Degree Name
Master of Science in Engineering (MSEgr)
Abstract
The digital world has been dominated by the growth of synchronous digital design techniques for last few decades. Traditional Boolean logic is symbolically incomplete since it has a separate control logic, time in the form of clock signal which be carefully integrated with the logic design, but with digital clock signal already in the GHz range, this integration is further complicated. One approach to address post GHz digital logic design is to use clockless or asynchronous digital design techniques. In the mid '90s Theaseus Logic Inc. proposed a method to design Asynchronous circuits using Null Convention Logic (NCL).This thesis introduces a technique for mapping NCL circuits and applications onto commercial-off-the-shelf (COTS) field programmable gate arrays (FPGAs). NCL logic was introduced as a four value logic (as opposed to the two valued standard Boolean) then transitioned to a three value logic, and finally to a two value logic which is similar to a two valued Boolean logic but with integrated control logic. We extend this theory to basic functional gates that can be implemented in FPGA functional look-up-tables (LUTs). To demonstrate the techniques we map basic adder circuits then extend that to a more complicated Fast Fourier Transform (FFT) circuit. All blocks were built and implemented on a Xilinx Virtex II pro FPGA. The circuits were tested using Modelsim and implemented using Xilinx Platform Studio.
Page Count
45
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2008
Copyright
Copyright 2008, all rights reserved. This open access ETD is published by Wright State University and OhioLINK.
