In-Situ Stress State Measurements During Chip-on-Board Assembly
Document Type
Article
Publication Date
1-1999
Abstract
In this work, die stresses in wire bonded chip-on-board (COB) packages have been measured using special [111] silicon stress test chips. The test die incorporate an array of optimized eight-element dual polarity piezoresistive sensor rosettes, which are uniquely capable of evaluating the complete stress state (six stress components) at points on the surface of the die. Sensor resistance measurements were recorded before packaging, after die attachment, and throughout the encapsulant cure process. Using the appropriate theoretical equations, the stresses at sites on the die surface have been calculated from the raw sensor resistance data. Also, three-dimensional (3-D) nonlinear finite element simulations of the chip-on-board packages were performed, and the stress predictions were correlated with the experimental test chip data.
Repository Citation
Zou, Y.,
Suhling, J. C.,
Johnson, R. W.,
Jaeger, R. C.,
& Mian, A.
(1999). In-Situ Stress State Measurements During Chip-on-Board Assembly. IEEE Transactions on Electronics Packaging Manufacturing, 22 (1), 38-52.
https://corescholar.libraries.wright.edu/mme/344
DOI
10.1109/6104.755088
