Publication Date
2017
Document Type
Thesis
Committee Members
Marian Kazimierczk (Committee Member), Saiyu Ren (Advisor), Raymond Siferd (Committee Member)
Degree Name
Master of Science in Electrical Engineering (MSEE)
Abstract
Analog to Digital Converters bridge the gap between physical world and digital signal processing. Most times analog signals received from the real world needs to be amplified and converted to digital to impart various signal enhancements to the received signal. The digital signal is much suitable to operate on with less noise and well defined logic levels when compared to continuously varying analog signal. Communication systems demand ever-increasing bandwidth which unfortunately has been a huge limitation for present day ADCs. Hence, an architecture which combines the accuracy of a SAR -ADC with the concept of pipelining to increase the bandwidth can be a great solution to achieve high sampling frequency (GHz) and broad bandwidth. The 8- bit SAP ADC implemented in this thesis using 90nm COMS technology achieves a sampling rate of 1GHz with input frequencies up to 125MHz
Page Count
61
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2017
Copyright
Copyright 2017, all rights reserved. My ETD will be available under the "Fair Use" terms of copyright law.
ORCID ID
0000-0002-9065-685X
