Publication Date
2023
Document Type
Thesis
Committee Members
Saiyu Ren, Ph.D. (Advisor); Yan Zhuang, Ph.D. (Committee Member); Raymond Siferd, Ph.D. (Committee Member)
Degree Name
Master of Science in Electrical Engineering (MSEE)
Abstract
Analog-to-Digital Converters (ADCs) are essential elements of most complex electronic devices. ADCs allow for an analog signal to be converted into the digital domain, and thus interpreted by a digital circuit or model. While ADCs are extremely common, they are not immune from common tradeoffs when being designed and implemented. The most prominent tradeoff when selecting or designing an ADC is whether to pursue a high conversion rate or a high resolution on the digital output. There are some ADC designs that allow for relatively high resolution while maintaining a respectable conversion rate, however these designs often come at the expense of implementation size and scalability concerns. This thesis presents the design of a new noise-canceller (NC) ADC architecture which is aimed at increasing the resolution of conventional high conversion rate ADCs. The NC ADC architecture utilizes a relatively low-resolution ADC which is already capable of operating at the desired high conversion rate; this is used as the first stage. To achieve the desired targeted resolution, a second stage, the noise-canceller (NC) adaptive filter is implemented. The NC adaptive filter functions to minimize the analog root-mean-square (RMS) error between the filter output, which is converted to an analog value, and the analog input. When this error is minimized, significant increases in spurious free dynamic range (SFDR) and effective number of bits (ENOB) can be measured at the adaptive filter output. A given ADC with 8 bits of functional resolution during standard operation was able to increase its functional resolution to 16 bits when the noise-canceller ADC architecture was used in a Simulink based FPGA-in-the-Loop (FIL) implementation on the Xilinx XCZ020 board. In a FIL implementation, an average ENOB increase of 8.337 was measured contributing to a total average ENOB of 16.098 at the NC ADC output, an increase of 107.41% when compared to the provided 8-bit ADCs fixed point output. The SFDR for this implementation increased to an average of 105.760 dBc, an increase of 91.83% when compared to the provided 8-bit ADCs fixed point output.
Page Count
83
Department or Program
Department of Electrical Engineering
Year Degree Awarded
2023
Copyright
Copyright 2023, some rights reserved. My ETD may be copied and distributed only for non-commercial purposes and may not be modified. All use must give me credit as the original author.
Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-No Derivative Works 4.0 International License.
ORCID ID
0009-0007-4093-6566
